View DSPB56720AG_4132120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Data Sheet: Technical Data
Document Number: DSP56720 Rev.1, 12/2007
DSP56720 / DSP56721
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
The Symphony DSP56720/DSP56721 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using multiple DSP56300 24-bit cores. The DSP56720/DSP56721 devices are intended for automotive, consumer, and professional audio applications that require high performance for audio processing. In addition, the DSP56720 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, HD-DVD and Blu-Ray players, car audio/amplifiers, and professional recording equipment. The DSP56720/DSP56721 devices excel at audio processing for automotive and consumer audio applications requiring high MIPs. Higher MIPs and memory requirements are driven by the new high-definition audio standards (Dolby Digital+, Dolby TrueHD, DTS-HD, for example) and the desire to process multiple audio streams. In addition, DSP56720/DSP56721 devices are optimal for the professional audio market requiring audio recording, signal processing, and digital audio synthesis. The DSP56720/DSP56721 processors provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56720/DSP56721 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56720 or DSP56721 device can replace dual-DSP designs, saving costs while meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/7x families are included, as well as a variety of new modules. Included among the new modules are an Asynchronous Sample Rate Converter (ASRC), Inter-Core
Device DSP56720 DSP56720
DSP56720 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitch DSP56721 80-Pin LQFP 14 mm x 14 mm 0.65 mm pitch 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitch
Ordering Information Device Marking or Operating Temperature Range DSPA56720AG DSPB56720AG DSPA56721AG DSPB56721AG DSPA56721AF DSPB56721AF LQFP Package 20 mm x 20 mm 20 mm x 20 mm 20 mm x 20 mm 20 mm x 20 mm 14 mm x 14 mm 14 mm x 14 mm
Communication (ICC), an External Memory Controller (EMC) to support SDRAM, and a Sony/Philips Digital Interface (S/PDIF). The DSP56720/DSP56721 offer 200 million instructions per second (MIPs) per core using an internal 200 MHz clock. The DSP56720/DSP56721 are high density CMOS devices with 3.3 V inputs and outputs. The DSP56720 device is slightly different than the DSP56721 device--the DSP56720 includes an external memory interface while the DSP56721 device does not. The DSP56720 block diagram is shown in Figure 1; the DSP56721 block diagram is shown in Figure 2.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2006, 2007. All rights reserved.
Table of Contents
1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .4 1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6 1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7 1.4 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . .10 2.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . .10 2.1.4 DC Electrical Characteristics . . . . . . . . . . . . . . .11 2.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . .12 2.1.6 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1.7 External Clock Operation. . . . . . . . . . . . . . . . . .13 2.1.8 Reset, Stop, Mode Select, and Interrupt Timing 14 2.2 Module-Level Specifications . . . . . . . . . . . . . . . . . . . . .17 2.2.1 Serial Host Interface (SHI) SPI Protocol Timing 18 2.2.2 Serial Host Interface (SHI) I2C Protocol Timing.24 2.2.3 Programming the SHI I2C Serial Clock . . . . . . 26 2.2.4 Enhanced Serial Audio Interface (ESAI) Timing 27 2.2.5 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.6 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.7 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.8 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35 2.2.9 Host Data Interface (HDI24) Timing . . . . . . . . . 35 2.2.10 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2.11 EMC Timing (DSP56720 only) . . . . . . . . . . . . . 43 Functional Description and Application Information . . . . . . . 48 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . 48 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . 48 6.2 144-Pin Package Outline Drawing . . . . . . . . . . . . . . . . 51 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2
3 4 5 6
7 8
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 2 Freescale Semiconductor
EXTAL/XTAL
Chip Config
ESAI_1
S/PDIF
WDT_1
ESAI_2
ESAI_3
TEC_1
GPIO
SHI_1
ESAI
WDT
DSP Core-0
On-Chip Memory
GPIO
EMC
CGM
ASRC
DSP Core-1
On-Chip Memory
Arbiter 9
Arbiter 8
P
X
Y
Shared Bus 0 Shared Bus 1
Arbiters 0-7
P
X
Y
PCU / AGU / ALU
DMA
OnCE
Shared Memory 8K Blocks 0-7 (64K total)
OnCE
PCU / AGU / ALU
DMA
MODA0, MODB0, MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1, MODC1, MODD1
Figure 1. DSP56720 Block Diagram
HDI24
EXTAL/XTAL
Chip Config
TIMER_1
HDI24_1
ESAI_1
TIMER
SPDIF
WDT_1
ESAI_2
ESAI_3
HDI24
GPIO
SHI_1
ESAI
WDT
DSP Core-0
On-Chip Memory
GPIO
CGM
ASRC
DSP Core-1
On-Chip Memory
Arbiter 8
Shared Bus 0 P X Y
Arbiters 0-7
Shared Bus 1 P X Y
PCU / AGU / ALU
DMA
OnCE
Shared Memory 8K Blocks 0-7 (64K total)
OnCE
PCU / AGU / ALU
DMA
MODA0, MODB0, MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1, MODC1, MODD1
Figure 2. DSP56721 Block Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 3
GPIO
SHI
GPIO
TEC
SHI
1
Pin Assignments
Table 1. Pin Assignments by Package
Device DSP56720 DSP56721 Package 144-pin plastic LQFP 80-pin plastic LQFP 144-pin plastic LQFP See Figure 3 on page 5 Figure 4 on page 6 Figure 5 on page 7
DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin assignments of a specific device in a specific package, please see sections 1.2-1.1.
For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).
1.1
Pinout for DSP56720 144-Pin Plastic LQFP Package
For the pinout of the DSP56720 144-pin plastic LQFP package, see Figure 3.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 4 Freescale Semiconductor
CORE_VDD CORE_GND LALE LCS0 LCS1 LCS2 LCS3 LCS4 LCS5 LCS6 LCS7 IO_VDD IO_GND CORE_VDD CORE_GND LWE LOE LGPL5 LSDA10 LCKE LCLK LBCTL LSDWE LSDCAS LGTA LA0 LA1 LA2 IO_VDD IO_GND PLLP1_GND PLLP1_VDD PLLD1_GND PLLD1_VDD PLLA1_GND PLLA1_VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
SCAN MODA0/IRQA MODB0/IRQB MODC0/PLOCK MODD0/PG1 FSR_3 SCKR_3 HCKR_3 SCKT_3 FST_3 HCKT_3 IO_GND IO_VDD CORE_GND CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 MODD1/PG2 SDO2_2/SDI3_2 SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 RESET CORE_GND CORE_VDD
DSP56720 144-Pin
IO_GND IO_VDD WDT PINIT/NMI TDO TDI TCK TMS SDO2_1/SDI3_1 SDO3_1/SDI2_1 SDO4_1/SDI1_1 SDO5_1/SDI0_1 CORE_GND CORE_VDD FSR SCKR HCKR SCKT FST HCKT SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 SPDIFOUT1 SPDIFIN1 IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 5
LSYNC_IN LSYNC_OUT LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 CORE_VDD CORE_GND IO_VDD IO_GND LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 IO_VDD IO_GND CORE_VDD CORE_GND LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 IO_GND IO_VDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 3. DSP56720 144-Pin Package Pinout
1.2
Pinout for DSP56721 80-Pin Plastic LQFP Package
For the pinout of the DSP56721 80-pin plastic LQFP package, see Figure 4.
MODC0/PLOCK
MODC1/NMI_1
MODA1/IRQC
MODB1/IRQD
MODA0/IRQA
MODB0/IRQB
CORE_GND
SS_1/HA2_1
CORE_GND 62
CORE_VDD
76
75
67
66
65
80
79
78
77
72
71
70
69
68
64
63
74
73
SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 IO_VDD IO_GND CORE_VDD CORE_GND SPDIFIN1/SDO2_2/SDI3_2 SPDIFOUT1/SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 FSR_3 SCKR_3 SCKT_3 GND GND GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 33 34 37 38 39 25 26 35 36 40
61 60 59 58 57 56 55 54
CORE_VDD
HREQ/PH4
IO_VDD
SS/HA2
MISO/SDA
MOSI/HA0
SCK/SCL
IO_GND
RESET
SCAN
WDT PINIT/NMI TDO TDI TCK TMS CORE_GND CORE_VDD SDO4/SDI1 SDO5/SDI0 IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD
DSP56721 80-Pin
53 52 51 50 49 48 47 46 45 44 43 42 41
SDO2_1/SDI3_1
SDO3_1/SDI2_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
CORE_GND
CORE_GND
CORE_VDD
CORE_VDD
SDO2/SDI3
Figure 4. DSP56721 80-Pin Package
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 6 Freescale Semiconductor
SDO3/SDI2
SCKR
FSR
IO_VDD
IO_GND
FST_3
HCKT_3
HCKR
SCKT
FST
HCKT
1.3
Pinout for DSP56721 144-Pin Plastic LQFP Package
For the pinout of the DSP56721 144-pin plastic LQFP package, see Figure 5.
TIO0/H15/HAD15 PG18/HDI_SEL IO_GND TIO0_1/H18/HAD18 CORE_VDD CORE_GND SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 IO_VDD IO_GND CORE_VDD CORE_GND SDO2_2/SDI3_2 SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 HCKR_3 FSR_3 SCKR_3 SCKT_3 IO_VDD IO_GND H6/HAD6 H7/HAD7 SPDIFIN2/H9/HAD9 SPDIFIN3/H10/HAD10 SPDIFIN4/H11/HAD11 SPDIFOUT2/H13/HAD13 SPLOCK/H14/HAD14 GND GND GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
SCAN MODA0/IRQA MODB0/IRQB MODC0/PLOCK MODD0/PG1 IO_GND IO_VDD CORE_GND CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 MODD1/PG2 FSR_2 SCKR_2 SCKT_2 FST_2 SDO0_2 SDO1_2 IO_GND IO_VDD SDO0_3 SDO1_3 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 HREQ_1/PH4_1 SCK_1/SCL_1 MOSI_1/HA0_1 MISO_1/SDA_1 RESET CORE_GND CORE_VDD
DSP56721 144-Pin
IO_GND IO_VDD WDT PIINT/NMI TDO TDI TCK TMS SCKR_1 FSR_1 SCKT_1 FST_1 SDO0_1 SDO1_1 IO_GND IO_VDD CORE_GND CORE_VDD SDO0 SDO1 SDO4/SDI1 SDO5/SDI0 SPDIFOUT1/H12/HAD12 SPDIFIN1/H8/HAD8 HACK/HRRQ HOREQ/HTRQ IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD
1.4
Pin Multiplexing
Many pins are multiplexed. For more about pin multiplexing, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 7
HAS/HA0 HA1/HA8 HA2/HA9 HRW/HRD HDS/HWR HCS/HA10 IO_VDD IO_GND FST_3 HCKT_3 SDO2_1/SDI3_1 SDO3_1/SDI2_1 CORE_VDD CORE_GND SDO4_1/SDI1_1 SDO5_1/SDI0_1 FSR SCKR HCKR SCKT IO_VDD IO_GND CORE_VDD CORE_GND FST HCKT SDO2/SDI3 SDO3/SDI2 IO_GND IO_VDD H0/HAD0 H1/HAD1 H2/HAD2 H3/HAD3 H4/HAD4 H5/HAD5
37 38 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 5. DSP56721 144-Pin Package Pinout
2
Electrical Characteristics
Table 2. Electrical Characteristics
For Section 2.1, "Chip-Level Conditions" Section 2.2, "Module-Level Specifications" See on page 8 on page 17
For electrical characteristics, see Table 2.
2.1
Chip-Level Conditions
Table 3. Chip-Level Conditions
For Section 2.1.1, "Maximum Ratings" Section 2.1.2, "Thermal Characteristics" Section 2.1.3, "Power Requirements" Section 2.1.4, "DC Electrical Characteristics" Section 2.1.5, "AC Electrical Characteristics" Section 2.1.6, "Internal Clocks" Section 2.1.7, "External Clock Operation" Section 2.1.8, "Reset, Stop, Mode Select, and Interrupt Timing" See on page 8 on page 10 on page 10 on page 11 on page 12 on page 12 on page 13 on page 14
For a summary of chip-level conditions in this section, see Table 3.
2.1.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (for example, either GND or VDD). The suggested value for a pull-up or pull-down resistor is 4.7 k.
For maximum ratings, see Table 4.
NOTE
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 8 Freescale Semiconductor
Table 4. Maximum Ratings
Rating1 Supply Voltage Symbol VCORE_VDD, VPLLD_VDD VPLLP_VDD, VIO_VDD, VPLLA_VDD, Maximum CORE_VDD power supply ramp time4 Input Voltage per pin excluding VDD and GND Current drain per pin excluding VDD and GND (Except for pads listed below) LSYNC_OUT LCLK LALE TDO Operating temperature range3 Storage temperature ESD protected voltage (Human Body Model) ESD protected voltage (Charged Device) * All pins * Corner pins Notes:
1. 2. 3. 4. GND = 0 V, TJ = -40C to 125C, CL = 50pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. Operating temperature qualified for consumer applications. TJ = TA + qJA x Power. Variables used were Core Current = 900mA, I/O Current = 200mA, Core Voltage = 1.1 V, I/O Voltage = 3.6 V, TA = 105C. If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous operation.
Value1, 2 -0.3 to + 1.26
Unit V
-0.3 to + 4.0 10 GND -0.3 to 5.5V 12 16 16 16 24 -40 to +125 -65 to +150 2000 500 750
V ms V mA mA mA mA mA
Tr VIN I Ilsync_out Ilclk Iale IJTAG TJ TSTG - -
C C
V V
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 9
2.1.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic Board Type Single layer board (1s) Four layer board (2s2p) RJA or JA Symbol LQFP Values 57 for 80 QFP 49 for 144 QFP 44 for 80 QFP 40 for 144 QFP Unit
For thermal characteristics, see Table 5.
Natural Convection, Junction-to-ambient thermal resistance1,2
C/W C/W C/W
Junction-to-case thermal resistance3 Notes:
1. 2. 3.
-
RJC or JC 10 for 80 QFP 9 for 144 QFP
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
2.1.3
Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins. IO_VDD External Schottky Diode
Core_VDD
Figure 6. Prevent High Current Conditions by Using External Schottky Diode If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead of Core_VDD, as shown in Figure 7.
Core_VDD
IO_VDD
Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms, as shown in Figure 8.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 10 Freescale Semiconductor
Tr
1.0V
Core_VDD 0 V Tr must be < 10 ms Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
2.1.4
DC Electrical Characteristics
Table 6. DC Electrical Characteristics
Characteristics Symbol VDD Min 0.9 Typ 1.0 Max 1.1 Unit V
For DC electrical characteristics, see Table 6.
Supply voltages * Core (Core_VDD) * PLL (PLLD_VDD, PLLD1_VDD) Supply voltages * I/O (IO_VDD) * PLL (PLLP_VDD, PLLP1_VDD) * PLL (PLLA_VDD, PLLA1_VDD) Input high voltage
VDDIO
3.14
3.3
3.46
V
VIH
2.0
-
VIO_VDD+2V
V
Note: To avoid a high current condition and possible system damage, all 3.3 volt supplies must rise before the 1.0 volt supplies rise. Input low voltage Input leakage current Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.3 V or 0 V) Output high voltage IOH = -12 mA LSYNC_OUT, LALE, LCLK Pins IOH = -16 mA, TDO Pin IOH = -24 mA Output low voltage IOL = 12 mA LSYNC_OUT, LALE, LCLK Pins IOL = 16 mA, TDO Pins IOL = 24 mA VIL IIN CIN ITSI VOH -10 2.4 -0.3 - - - 18 - - 10 - 0.8 84 V A pF A V
VOL
-
-
0.4
V
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 11
Table 6. DC Electrical Characteristics (Continued)
Characteristics Internal supply current1 (core only) at internal clock of 200 MHz * In Normal mode * In Wait mode * In Stop mode2 Symbol Min Typ Max Unit
ICCI ICCW ICCS CIN
- - - -
190 90 50 -
780 680 640 10
mA mA mA pF
Input capacitance Notes:
1.
2.
The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.0V, VDD_IO = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCORE_VDD = 1.10V, VIO_VDD) = 3.6V at TJ = 125C. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
2.1.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56720/DSP56721 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.
2.1.6
Internal Clocks
Table 7. Internal Clocks
Internal clock characteristics are listed in Table 7.
No. 1 2 3 4
Characteristics Comparison Frequency Input Clock Frequency PLL VCO Frequency Output Clock Frequency * with PLL enabled * with PLL disabled Duty Cycle
[1]
Symbol Fref Fin Fvco Fout
Min 2
Typ - Max = 200 MHz
Max 8
Unit MHz
Condition Fref = Fin/NR
200 25 -
- -
400 200 200
MHz MHz
Fvco = (Fin * NF)/NR Fout= Fvco/NO Fout = Fin
5 Notes:
-
40
50
60
%
Fvco= 200 MHz - 400 MHz
Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 12 Freescale Semiconductor
2.1.7
External Clock Operation
The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.
EXTAL XTAL Suggested component values: Fosc = 24.576 MHz R = 1 M 10% C (EXTAL)= 18 pF C (XTAL) = 18 pF C Calculations are for a 5 - 30 MHz crystal with the following parameters: * Shunt capacitance (C0) of 10 pF - 12 pF * Series resistance 40 Ohm * Drive level of 10 W
R
C
XTAL1
Figure 9. Using the On-Chip Oscillator If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used.
VIH EXTAL VIL
ETH ETL
Midpoint
1 3
2
ETC
Note:
The midpoint is 0.5 (VIH + VIL).
Figure 10. External Clock Timing Table 8. Clock Operation
No. 1 Characteristics EXTAL input high 1 (40% to 60% duty cycle) * Crystal oscillator * Square wave input Symbol Min Max Units
Eth
16.67 2.5
100 inf
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 13
Table 8. Clock Operation (Continued)
No. 2 Characteristics EXTAL input low1 (40% to 60% duty cycle) * Crystal oscillator * Square wave input EXTAL cycle time * With PLL disabled * With PLL enabled Instruction cycle time * With PLL disabled * With PLL enabled Symbol Min Max Units
Etl
16.67 2.5 5 33.3 5.00 5.00
100 inf inf 500 inf 5120
ns
3
Etc
ns
4
Tc
ns
Notes:
1. 2. Measured at 50% of the input transition. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56720/DSP56721 being powered up.
3.
2.1.8
Reset, Stop, Mode Select, and Interrupt Timing
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
For reset, stop, mode select, and interrupt timing, see Table 9.
No. 10 11
Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled Syn reset deassert delay time * Minimum * Maximum (PLL enabled)
Expression - 2 x TC 2 x TC 2 x TC (2 x TC) + TLOCK - - - - 10 x TC + 4
Min - 10 10 10 200 10.0 10.0 4 4 54
Max 11 - - - - - - - - -
Unit ns ns ns ns us ns ns ns ns ns
13
14 15 16 17 18
Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from interrupt trigger to interrupt code execution
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 14 Freescale Semiconductor
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
No. 19 Characteristics Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution1 Interrupt Requests Rate1 * ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1 * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 22 DMA Requests Rate * Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 * Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 * Timer, Timer_1 * IRQ, NMI (edge trigger) Notes:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 s. Periodically sampled and not 100% tested. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration.
Expression
Min
Max
Unit
(128K x TC) 25 x TC (128K x TC) + TLOCK (25 x TC) + TLOCK 10 x TC + 3.8
655 125 855 200 -
- - - - 53.8
s ns s s ns
21
12 x TC 8 x TC 8 x TC 12 x TC 6 x TC 7 x TC 2 x TC 3 x TC
- - - - - - - -
60.0 40.0 40.0 60.0 30.0 35.0 10.0 15.0
ns ns ns ns ns ns ns ns
2.
3. 4.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 15
VIH RESET
11 10
All Pins Reset Value
13
Figure 11. Reset Timing Diagram a) First Interrupt Instruction Execution 19 18
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
b) General Purpose I/O
General Purpose I/O
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
20
Figure 12. External Fast Interrupt Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 16 Freescale Semiconductor
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
16
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
17
Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)
RESET
VIH
14 15
MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQC,IRQD, NMI
Figure 14. MODE Select Set-Up and Hold Timing Diagram
2.2
Module-Level Specifications
Table 10. Module-Level Specifications
For Section 2.2.1, "Serial Host Interface (SHI) SPI Protocol Timing" Section 2.2.2, "Serial Host Interface (SHI) I Section 2.2.3, "Programming the SHI I
2C 2C
For a summary of the module-level specifications in this section, see Table 10.
See on page 18 on page 24 on page 26 on page 27 on page 32 on page 32 on page 33 on page 35 on page 35 on page 42 on page 43
Protocol Timing"
Serial Clock"
Section 2.2.4, "Enhanced Serial Audio Interface (ESAI) Timing" Section 2.2.5, "Timer Timing" Section 2.2.6, "GPIO Timing" Section 2.2.7, "JTAG Timing" Section 2.2.8, "Watchdog Timer Timing" Section 2.2.9, "Host Data Interface (HDI24) Timing" Section 2.2.10, "S/PDIF Timing" Section 2.2.11, "EMC Timing (DSP56720 only)"
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 17
2.2.1
Serial Host Interface (SHI) SPI Protocol Timing
Table 11. Serial Host Interface SPI Protocol Timing Parameters
See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams.
No. 23
Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min)
Mode Master/Slave
Filter Mode Bypassed Very Narrow Narrow Wide
Expression 10 x TC + 9 10 x TC + 9 10 x TC + 133 10 x TC + 333 - - - - 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 2.5 x TC + 12 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 0.5 x (tSPICC -10) 2.5 x TC + 12 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 - -
Min 59.0 59.0 183.0 373.0 - - - - 33.0 33.0 86.0 121.5 22.5 22.5 114.5 201.5 33.0 33.0 86.0 121.5 22.5 22.5 114.5 201.5 - -
Max - - - - 0 10 50 100 - - - - - - - - - - - - - - - - - 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
XX Tolerable Spike width on data or clock in
-
Bypassed Very Narrow Narrow Wide
24
Serial clock high period
Master
Bypassed Very Narrow Narrow Wide
Slave
Bypassed Very Narrow Narrow Wide
25
Serial clock low period
Master
Bypassed Very Narrow Narrow Wide
Slave
Bypassed Very Narrow Narrow Wide
26
Serial clock rise/fall time
Master Slave
- -
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 18 Freescale Semiconductor
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
No. 27 Characteristics1,3,4 SS assertion to first SCK edge CPHA = 0 Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide CPHA = 1 Slave Bypassed Very Narrow Narrow Wide 28 Last SCK edge to SS not asserted Slave Bypassed Very Narrow Narrow Wide 29 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed Very Narrow Narrow Wide 30 SCK last sampling edge to data input not valid Master /Slave Bypassed Very Narrow Narrow Wide 31 32 33 SS assertion to data out active SS deassertion to data high impedance2 SCK edge to data out valid (data out delay time) Slave Slave Master /Slave - - Bypassed Very Narrow Narrow Wide 34 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed Very Narrow Narrow Wide 35 SS assertion to data out valid (CPHA = 0) Slave - Expression 3.5 x TC+15 3.5 x TC+5 - - - - - - - - - - - - - - 2 x TC + 10 2 x TC + 30 2 x TC + 60 - - - - - - - - - - - - Min 32.5 22.5 0 0 10 0 0 0 12 22 100 200 0 0 0 0 10 40 70 100.0 5 - - - - - 11.67 15 55 105 - Max - - - - - - - - - - - - - - - - - - - - - 9 46.2 270 376 521 - - - - 14.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 19
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
No. 36 Characteristics1,3,4 First SCK sampling edge to HREQ output deassertion Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Very Narrow Narrow Wide 38 39 40 41 42 43
1. 2. 3. 4. 5.
Expression - - - - - - - - - TC + 6 0.5 x TSPICC + 3.0 x TC + 43 - - 3.0 x TC
Min 45 55 95 145 50.0 60.0 100.0 150.0 45.0 11.0 96.0 0 0 15
Max - - - - - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) HREQ assertion width
Slave Slave Master Master Master Master
- - - - - -
Notes:
VCORE_VDD = 1.0 0.10 V; TJ = -40C to 125C; CL = 50 pF. Periodically sampled, not 100% tested. All times assume noise free inputs. All times assume internal clock frequency of 200 MHz. SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 20 Freescale Semiconductor
SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 MISO (Input)
MSB Valid
23 26 26
26
23 26
30
29
LSB Valid
30
33 MOSI (Output) 40 HREQ (Input) 43 MSB 42
34 LSB
Figure 15. SPI Master Timing Diagram (CPHA = 0)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 21
SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 30 MISO (Input)
MSB Valid LSB Valid
23 26 26
26
23 26 29 30
29
33 MOSI (Output) 40 42 HREQ (Input) 43 Figure 16. SPI Master Timing Diagram (CPHA = 1) MSB 41
34 LSB
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 22 Freescale Semiconductor
SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 SCK (CPOL = 1) (Input) 35 31 MISO (Output) 29 30 MOSI (Input) HREQ (Output) Figure 17. SPI Slave Timing Diagram (CPHA = 0)
MSB Valid LSB Valid
23 26 26 39
28
24 25
26
23 26
34 MSB
33
34
32 LSB 29 30
36
38
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 23
SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 SCK (CPOL = 1) (Input) 33 MISO (Output) 31 MSB 29 30 MOSI (Input) HREQ (Output) Figure 18. SPI Slave Timing Diagram (CPHA = 1)
MSB Valid LSB Valid
23 26 26
28
24 25
26
26
33
34
32 LSB 29 30
36
37
2.2.2
Serial Host Interface (SHI) I2C Protocol Timing
Table 12. SHI I2C Protocol Timing Parameters
Standard I2C Characteristics1,2,3,4,5 Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Filters enabled. 44 44 45 46 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time Symbol/ Expression - - - - - FSCL TSCL TBUF TSUSTA - 10 4.7 4.7 0 10 50 100 100 - - - - - - - - 2.5 1.3 0.6 0 10 50 100 400 - - - ns ns ns ns kHz s s s Standard Min Max Fast-Mode Unit Min Max
See Table 12 for SHI I2C protocol timing parameters and Figure 19 for the timing diagram.
No.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 24 Freescale Semiconductor
Table 12. SHI I2C Protocol Timing Parameters (Continued)
Standard I2C Characteristics1,2,3,4,5 Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time DSP clock frequency * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled HREQ in assertion to first SCL edge * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled First SCL edge to HREQ is not asserted (HREQ in hold time.)
1. 2. 3. 4. 5. 6.
No. 47 48 49 50 51 52 53 54
Symbol/ Expression THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT FOSC
Standard Min 4.0 4.7 4.0 - - 250 0.0 10.6 10.6 11.8 13.1 Max - - - 5.0 5.0 - - - - - - 3.4 - -
Fast-Mode Unit Min 0.6 1.3 1.3 - - 100 0.0 28.5 28.5 39.7 61.0 - 0.6 0.0 Max - - - 5.0 5.0 - 0.9 - - - - 0.9 - - s s s ns ns ns s MHz MHz MHz MHz s s ns
55 56 57 58
TVD;DAT TSU;STO tSU;RQI TNG;RQO 4 x TC + 30 4 x TC + 50 4 x TC + 130 4 x TC + 230 TAS;RQO 2 x TC + 30 2 x TC + 40 2 x TC + 80 2 x TC + 130 TAS;RQI
- 4.0 0.0
- - - -
50.0 70.0 250.0 150.0
- - - -
50.0 70.0 150.0 250.0
ns ns ns ns
59
40 50 90 140 4327 4317 4282 4227
- - - - - - - - -
40 50 90 140 927 917 877 827 0.0
- - - - - - - - -
ns ns ns ns ns ns ns ns ns
60
61
tHO;RQI
0.0
Notes:
VCORE_VDD = 1.00 0.10 V; TJ = -40C to 125C; CL = 50 pF. Pull-up resistor: R P (min) = 1.5K Ohms. Capacitive load: C b (max) = 50 pF. All times assume noise free inputs. All times assume internal clock frequency of 200 MHz. SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 25
2.2.3
Programming the SHI I2C Serial Clock
The programmed serial clock cycle, T I2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] where -- HRS is the pre scaler rate select bit. When HRS is cleared, the fixed divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC (if HDM[7:0] = $02 and HRS = 1) to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) Eqn. 3 Eqn. 2 Eqn. 1
The programmed serial clock cycle (TI2CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Equation 4. TI2CCP + 3 x TC + 45ns + TR
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
Eqn. 4
44 46
SCL
49
48
50 45
SDA
Stop Start
51 52
MSB
53
LSB
ACK
Stop
47 60
HREQ
58 61 57
55
56 59
Figure 19. I2C Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 26 Freescale Semiconductor
2.2.4
Enhanced Serial Audio Interface (ESAI) Timing
Table 13. Enhanced Serial Audio Interface Timing Parameters
See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams.
No. 62 63 Clock cycle5
Characteristics1, 3, 4
Symbol tSSICC
Expression5 4 x Tc 4 x Tc 2 x Tc 2 x Tc
Min 20.0 20.0 10 10 10 10 - - - - - - - - - - - - 12.0 19.0 3.5 9.0 2.0 12.0 2.0 12.0 2.5 8.5 0.0 19.0 6.0 0.0 - - - -
Max - - - - - - 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 17.0 7.0 - - - - - - - - - - - - - - 18.0 8.0 20.0 10.0
Condition2 Unit i ck i ck - - ns - - x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Clock high period * For internal clock * For external clock
-
64
Clock low period * For internal clock * For external clock
-
2 x Tc 2 x Tc
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
SCKR rising edge to FSR out (bl) high SCKR rising edge to FSR out (bl) low SCKR rising edge to FSR out (wr) high6 SCKR rising edge to FSR out (wr) low6 SCKR rising edge to FSR out (wl) high SCKR rising edge to FSR out (wl) low Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge FSR input (bl, wr) high before SCKR falling edge 6 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge Flags input setup before SCKR falling edge Flags input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high SCKT rising edge to FST out (bl) low
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 27
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No. 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Characteristics1, 3, 4 SCKT rising edge to FST out (wr) high6 SCKT rising edge to FST out (wr) low6 SCKT rising edge to FST out (wl) high SCKT rising edge to FST out (wl) low SCKT rising edge to data out enable from high impedance SCKT rising edge to transmitter #0 drive enable assertion SCKT rising edge to data out valid SCKT rising edge to data out high impedance7 SCKT rising edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before SCKT falling edge6 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion Flag output valid after SCKT rising edge Symbol - - - - - - - - - - - - - - - Expression5 - - - - - - - - - - - - - - - Min - - - - - - - - - - - - - - - - - - 2.0 18.0 2.0 18.0 4.0 5.0 - - - - Max 20.0 10.0 22.0 12.0 19.0 9.0 20.0 10.0 22.0 17.0 17.0 11.0 18.0 13.0 21.0 16.0 14.0 9.0 - - - - - - 21.0 14.0 14.0 9.0 Condition2 Unit x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck - - x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 28 Freescale Semiconductor
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No. 95 96 97
1. 2.
Characteristics1, 3, 4 HCKR/HCKT clock cycle HCKT input rising edge to SCKT output HCKR input rising edge to SCKR output
Symbol - - -
Expression5 2 x TC - -
Min 10 - -
Max - 18.0 18.0
Condition2 Unit - - - ns ns ns
Notes:
VCORE_VDD = 1.00 0.10 V; TJ = -40C to 125C; CL = 50 pF. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (Asynchronous implies that SCKT and SCKR are two different clocks.) i ck s = internal clock, synchronous mode (Synchronous implies that SCKT and SCKR are the same clock.) bl = bit length wl = word length wr = word length relative SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Tc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
3.
4.
5. 6.
7. 8.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 29
62 63
SCKT (Input/Output)
64
78
FST (Bit) Out
79
82
FST (Word) Out
83
86 84
Data Out Transmitter #0 Drive Enable (Internal Signal)
86 87
First Bit Last Bit
93
89 91
FST (Bit) In
85
88
92 90
FST (Word) In
91
94
Flags Out
See Note
Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 20. ESAI Transmitter Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 30 Freescale Semiconductor
62 63
SCKR (Input/Output)
64 65 66
FSR (Bit) Out
69
FSR (Word) Out
70
71
Data In First Bit
72
Last Bit
73
FSR (Bit) In
75
74
FSR (Word) In
75
76
Flags In
77
Figure 21. ESAI Receiver Timing Diagram
HCKT
SCKT (Output)
95 96 Figure 22. ESAI HCKT Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 31
HCKR
SCKR (Output)
95 97 Figure 23. ESAI HCKR Timing
2.2.5
Timer Timing
Table 14. Timer Timing Parameters
No. 98 99 Notes:
1. 2. VCORE_VDD = 1.00 V 0.10 V; TJ = -40C to 125C, CL = 50 pF TIMER_1 specs match those of TIMER
See Table 14 for timer timing parameters and Figure 24 for the timing diagram.
Characteristics TIO Low TIO High
Expression Min 2 x TC + 2.0 2 x TC + 2.0 12.0 12.0 Max - -
Unit ns ns
TIO
98
99
Figure 24. TIO Timer Event Input Restrictions Diagram
2.2.6
GPIO Timing
Table 15. GPIO Timing Parameters
No. 100 101 102 103 104 Characteristics1 Fsys edge to GPIO out valid (GPIO out delay time)2 Fsys edge to GPIO out not valid (GPIO out hold time) Fsys In valid to EXTAL edge (GPIO in set-up time) Fsys edge to GPIO in not valid (GPIO in hold Minimum GPIO pulse high width
2 2
See Table 15 for general purpose input and output (GPIO) timing and Figure 25 for the timing diagram.
Expression - - - - 2 x TC
Min - - 2 0 10
Max 7 7 - - -
Unit ns ns ns ns ns
time)2
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 32 Freescale Semiconductor
Table 15. GPIO Timing (Continued)Parameters
No. 105 106 107 Notes:
1. VCORE_VDD = 1.0 V 0.10 V; TJ = -40C to 125C; CL = 50 pF
Characteristics1 Minimum GPIO pulse low width GPIO out rise time GPIO out fall time
Expression 2 x TC - -
Min 10 - -
Max - 13.0 13.0
Unit ns ns ns
Fsys
100 101
GPIO (Output)
102
GPIO Input) Valid
103
GPIO (Output)
104 106
105 107
Figure 25. GPIO Timing Diagram
2.2.7
JTAG Timing
Table 16. JTAG Timing Parameters
All Frequencies No. 108 109 110 111 112 113 114 115 Characteristics Min TCK frequency of operation (1/(TC x 3); maximum 10 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.65 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance - 100.0 50.0 - 15.0 24.0 - - Max 10.0 - - 3.0 - - 40.0 40.0 MHz ns ns ns ns ns ns ns Unit
See Table 16 for joint test action group (JTAG) timing parameters, and Figure 26, Figure 27, and Figure 28 for timing diagrams.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 33
Table 16. JTAG Timing Parameters (Continued)
All Frequencies No. 116 117 118 119 Notes:
1. 2. VCORE_VDD = 1.0 V 0.10 V; TJ = -40C to 125C , CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
Characteristics Min TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 5.0 25.0 - - Max - - 44.0 44.0
Unit ns ns ns ns
109
TCK (Input)
110
VIH VIL VM
110
VM
111
111
Figure 26. Test Clock Input Timing Diagram
TCK (Input)
VIL 112
VIH 113
Data Inputs
Input Data Valid
114
Data Outputs Output Data Valid
115
Data Outputs
114
Data Outputs Output Data Valid
Figure 27. Debugger Port Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 34 Freescale Semiconductor
TCK (Input) TDI TMS (Input)
VIH VIL 116
Input Data Valid
117
118
TDO (Output) Output Data Valid
119
TDO (Output)
118
TDO (Output) Output Data Valid
Figure 28. Test Access Port Timing Diagram
2.2.8
Watchdog Timer Timing
Table 17. Watchdog Timer Timing Parameters
For watchdog timer timing, see Table 17.
No. 120 121
Characteristics Delay from time-out to fall of WDT, WDT_1 Delay from timer clear to rise of WDT, WDT_1
Expression 2 x Tc 2 x Tc
Min 10.0 10.0
Max - -
Unit ns ns
2.2.9
Host Data Interface (HDI24) Timing
The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits of the HDI24 interface are pinned out on the DSP56721 device. See Table 18 for HDI24 timing and Figure 29, Figure 30, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 for timing diagrams. Table 18. HDI24 Timing Parameters
No. Characteristics2 Read data strobe assertion width3 HACK read assertion width Read data strobe deassertion width3 HACK read deassertion width Read data strobe deassertion width3 after "Last Data Register" reads4,5, or between two consecutive CVR, ICR, or ISR reads6 HACK deassertion width after "Last Data Register" reads4,5 200 MHz Expression Min 317 318 319 TC + 9.9 - 2 x TC + 6.6 14.9 9.9 16.6 Max - - - ns ns ns Unit
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 35
Table 18. HDI24 Timing Parameters (Continued)
No. Characteristics2 Write data strobe assertion width7 HACK write assertion width Write data strobe deassertion width7 HACK write deassertion width * after ICR, CVR and "Last Data Register" writes4 * after IVR writes, or * after TXH:TXM writes (with HBE=0), or * after TXL:TXM writes (with HBE=1) 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 HAS assertion width HAS deassertion to data strobe assertion8 Host data input setup time before write data strobe deassertion7 Host data input setup time before HACK write deassertion Host data input hold time after write data strobe deassertion7 Host data input hold time after HACK write deassertion Read data strobe assertion to output data active from high impedance3 HACK read assertion to output data active from high impedance Read data strobe assertion to output data valid3 HACK read assertion to output data valid Read data strobe deassertion to output data high impedance3 HACK read deassertion to output data high impedance Output data hold time after read data strobe deassertion3 Output data hold time after HACK read deassertion HCS assertion to read data strobe deassertion3 HCS assertion to write data strobe deassertion HCS assertion to output data valid HCS hold time after data strobe deassertion8 Address (AD7-AD0) setup time before HAS deassertion (HMUX=1) Address (AD7-AD0) hold time after HAS deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion8 * Read * Write 337 338 A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion8 Delay from read data strobe deassertion to host request assertion for "Last Data Register" read3, 4, 9
7
200 MHz Expression Min Max - - ns ns Unit
320 321
- 2 x TC + 6.6
13.2 16.6
-
16.5
-
- - - - - - - - TC + 9.9 - - - - - -
9.9 0.0 9.9 3.3 3.3 - - 3.3 14.9 9.9 - 0.0 4.7 3.3 0
- - - - - 24.2 9.9 - - - 19.1 - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
- - TC
4.7 3.3 5.0
- - - ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 36 Freescale Semiconductor
Table 18. HDI24 Timing Parameters (Continued)
No. Characteristics2 200 MHz Expression Min 339 340 Delay from write data strobe deassertion to host request assertion for "Last Data Register" write4, 7, 9 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 0)4, 8, 9 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 1, open drain Host Request)4, 8, 9, 10 Delay from DMA HACK deassertion to HOREQ assertion * For "Last Data Register" read4 * For "Last Data Register" write4 * For other cases 343 344 Delay from DMA HACK assertion to HOREQ deassertion * HROD = 04 Delay from DMA HACK assertion to HOREQ deassertion for "Last Data Register" read or write * HROD = 1, open drain Host Request4, 10
1. 2. 3. 4. 5.
Unit Max - 19.1 ns ns
2 x TC -
10.0 -
341
-
-
300.0
ns
342
ns 2 x TC + 19.1 1 x TC + 19.1 - - - 29.1 24.1 0.0 - - - - - 20.2 300.0 ns ns
Notes:
In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 1.0 V 10%; TJ = -40C to +125C; CL = 50 pF. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. 6. This timing is applicable only if two consecutive reads from one of these registers are executed. 7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode. 11. HDI24_1 specs match those of HDI24.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 37
317 HACK 327 326 HD23-HD0 329 328
318
HOREQ
Figure 29. HDI24 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 HD0-HD23 340 341 HOREQ, HRRQ, HTRQ 338 319 329
Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 38 Freescale Semiconductor
HA0-HA2 336 331 333 HCS 337
320 HWR, HDS 321 324 325 HD0-HD23 340 341 HOREQ, HRRQ, HTRQ 339
Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 39
HA8-HA10 336 322 HAS 323 337
317 HRD, HDS 334 335 327 328 329 HAD0-HAD23 Address 326 340 341 HOREQ, HRRQ, HTRQ 338 Data 318 319
Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 40 Freescale Semiconductor
HA8-HA10 336
322 HAS
323
320 HWR, HDS 334 335 HAD0-HAD23 Address 340 341 HOREQ, Data 339 324 321 325
HRRQ, HTRQ Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus
HOREQ (Output) 343 344 320 HACK (Input) TXH/M/L Write 324 325 H0-H23 (Input) Data Valid 342
321
Figure 34. HDI24 Host DMA Write Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 41
HOREQ (Output) 343 342 317 HACK (Input) 327 326 H0-H23 (Output) Data Valid RXH Read 328 329 318 342
Figure 35. HDI24 Host DMA Read Timing Diagram
2.2.10
S/PDIF Timing
See Table 19 for Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 for timing diagrams. Table 19. S/PDIF Timing Parameters
All Frequency Characteristics Symbol Min SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew: asynchronous inputs, no specs apply SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf) * Skew * Transition Risng * Transition Falling SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf) * Skew * Transition Risng * Transition Falling SRCK period SRCK high period SRCK low period STCLK period STCLK high period STCLK low period - - Max 0.7 ns Unit
- - - - - - srckp srckph srckpl stclkp stclkph stclkpl
- - -
1.5 24.2 31.3
ns
- - - 40.0 16.0 16.0 40.0 16.0 16.0
1.5 13.6 18.0 - - - - - -
ns
ns ns ns ns ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 42 Freescale Semiconductor
srckp srckpl SRCK (Output)
VM
srckph
VM
Figure 36. S/PDIF SRCK Timing Diagram
stclkp stclkpl STCLK (Input)
VM
stclkph
VM
Figure 37. S/PIDF STCLK Timing Diagram
2.2.11
EMC Timing (DSP56720 only)
The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 20, Table 21, and Table 22; for timing diagrams, see Figure 38, Figure 39, and Figure 40. Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Parameter LCLK cycle time LCLK skew to LSYNC_OUT Input setup to LSYNC_IN (except LGTA/LUPWAIT) Input hold from LSYNC_IN (except LGTA/LUPWAIT) LGTA valid time LUPWAIT valid time LALE negedge to LAD(address phase) invaild (address latch hold time) LALE valid time Output setup from LSYNC_IN (except LAD[23:0] and LALE) Output hold from LSYNC_IN (except LAD[23:0] and LALE) LAD[23:0] output setup from LSYNC_IN LAD[23:0] output hold from LSYNC_IN LSYNC_IN to output high impedance for LAD[23:0] Symbol Tclk Tclk_skew Tin_s Tin_h Tgta Tupwait Tale_h Tale Tout_s Tout_h Tad_s Tad_h Tad_z Min 10 - 2 2 12 12 3 3.8 4 2 3.5 1.5 - Max - 160 - - - - - - - - - - 4.3 Unit ns ps ns ns ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 43
Tclk
LCLK
Tclk_skew
LSYNC_OUT
Tsync_in_skew
LSYNC_IN
Tin_s Tin_h
LAD[23:0] (data)
asynchronous input
Tgta
LGTA
asynchronous input
Tupwait
LUPWAIT
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 44 Freescale Semiconductor
Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Parameter LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA/LUPWAIT)1 LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time Output setup from LCLK (except LAD[23:0] and LALE) Output hold from LCLK (except LAD[23:0] and LALE) LAD[23:0] output setup from LCLK LAD[23:0] output hold from LCLK LCLK to output high impedance for LAD[23:0] Symbol Tclk Tin_s Tin_h Tgta Tupwait Tale_h Tale Tout_s Tout_h Tad_s Tad_h Tad_z Min 20 8 -1 22 22 4 14 9 8 8 7 - Max - - - - - - - - - - - 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 45
Tclk
LCLK
Tin_s Tin_h
LAD[23:0] (data)
input
Tgta
LGTA
input
Tupwait
LUPWAIT
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4) Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Parameter LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time Output setup from LCLK (except LAD[23:0] and LALE) Output hold from LCLK (except LAD[23:0] and LALE) LGTA/LUPWAIT)1 Symbol Tclk Tin_s Tin_h Tgta Tupwait Tale_h Tale Tout_s Tout_h Min 40 8 -1 42 42 5 34 19 18 Max - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 46 Freescale Semiconductor
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)
Parameter LAD[23:0] output setup from LCLK LAD[23:0] output hold from LCLK LCLK to output high impedance for LAD[23:0] Symbol Tad_s Tad_h Tad_z Min 18 17 - Max - - 19 Unit ns ns ns
Notes: 1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
Tclk
LCLK
Tin_s Tin_h
LAD[23:0] (data)
input
Tgta
LGTA
input
Tupwait
LUPWAIT
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 47
3 4 5
Functional Description and Application Information Hardware Design Considerations Ordering Information
Table 23. Ordering Information
Product DSP56720 ROM Version A B DSP56721 A B A B Package 144-pin plastic LQFP 144-pin plastic LQFP 144-pin plastic LQFP 144-pin plastic LQFP 80-pin plastic LQFP 80-pin plastic LQFP Part Number DSPA56720AG DSPB56720AG DSPA56721AG DSPB56721AG DSPA56721AF DSPB56721AF
See the DSP56720 Reference Manual (DSP56720RM) for detailed functional and applications information.
For design considerations, also see Section 2.1.3, "Power Requirements."
Table 23 provides ordering information for both the DSP56720 and DSP56721.
6
Package Information
Table 24. Package Outline Drawings
Device DSP56720 DSP56721 Package 144-pin plastic LQFP 80-pin plastic LQFP 144-pin plastic LQFP See Figure 43 on page 51 and Figure 44 on page 52 Figure 41 on page 49 and Figure 42 on page 50 Figure 43 on page 51 and Figure 44 on page 52
For the outline drawings of available device packages, see Table 24 and sections 6.1-6.2.
6.1
80-Pin Package Outline Drawing
For the 80-pin package outline drawings, see Figure 41 and Figure 42.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 48 Freescale Semiconductor
Figure 41. 80-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 49
Figure 42. 80-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 50 Freescale Semiconductor
6.2
144-Pin Package Outline Drawing
For the 144-pin package drawings, see figures Figure 43 and Figure 44.
Figure 43. 144-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 51
Figure 44. 144-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 52 Freescale Semiconductor
7
Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc. distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). The following documents are required for a complete description of the device and are necessary to design properly with the parts: DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set. DSP56720/DSP56721 Reference Manual (document number DSP56720RM). Detailed description of memory, peripherals, and interfaces. DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device. DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device.
8
Revision History
Table 25. Revision History
Revision 1 Date December 2007 * Initial public release. Description
Table 25 summarizes revisions to this document.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 53
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org (c) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
Document Number: DSP56720
Rev.1 12/2007

▲Up To Search▲

Price & Availability of DSPB56720AG

	To Download DSPB56720AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .